[{"data":1,"prerenderedAt":114},["ShallowReactive",2],{"finding:a-1-ssim-tile-shader-investigation":3,"finding-runs:a-1-ssim-tile-shader-investigation":94,"finding-related:a-1-ssim-tile-shader-investigation":95},{"meta":4,"impact":27,"sections":32},{"id":5,"title":6,"subtitle":7,"eyebrow":8,"date":9,"status":10,"category":11,"polarity":12,"axes":13,"tags":15,"task_code":23,"related_runs":24,"related_findings":25},"a-1-ssim-tile-shader-investigation","A.1 SSIM タイルシェーダ — 実装試行せず documented investigation で close","TBDR imageblock_data を用いた SSIM tile shader 化は render-pipeline 大改修を伴い卒論完成までの時間枠で見合わず。卒論 第 3 軸 (Apple Silicon 固有最適化) に必要要件を記録する形で close。","Investigation · Apple TBDR","2026-05-23","stable","spec","negative",[14],3,[16,17,18,19,20,21,22],"phase-5","ssim","tbdr","metal","imageblock","investigation","deferred","A.1",[],[26],"a-10-kahan-negative",{"summary":28,"rank":29,"verdict":30,"delta_wallclock":31},"TBDR imageblock_data ベースの SSIM tile shader 化は render pipeline 大改修 + backward 設計 + 既存テスト 23 件への影響が大きく、卒論 time-box では見合わない。必要要件のみ記録して close。期待効果は SSIM kernel -50% \u002F trainer 全体 -3〜5%。","mid","investigative","expected -3〜5% (未検証)",[33,36,41,44,47,53,55,62,64,70,72,80,82,84,87,89],{"type":34,"text":35},"lead","TBDR \u003Ccode>imageblock_data\u003C\u002Fcode> を用いた SSIM tile shader 化は \u003Cstrong>render-pipeline 大改修\u003C\u002Fstrong> を伴い卒論完成までの時間枠で見合わない。卒論 第 3 軸 (Apple Silicon 固有最適化) のセクションに「TBD: 試行せず、必要要件を記録」として残す。",{"type":37,"label":38,"variant":39,"text":40},"callout","ユーザー判断 (2026-05-23)","info","A.1 は investigation doc で close、実装はしない。",{"type":42,"text":43},"heading","なぜ scope 大か",{"type":45,"text":46},"paragraph","現状の SSIM は通常の compute kernel (\u003Ccode>splat\u002Fshaders\u002Floss\u002Fssim.metal\u003C\u002Fcode>、164 行):",{"type":48,"items":49},"list",[50,51,52],"\u003Ccode>mean \u002F variance \u002F covariance\u003C\u002Fcode> を per-pixel に compute kernel で計算","7x7 window で gaussian blur (separable conv) を 2 段","compute pipeline state、threadgroup memory に依存",{"type":45,"text":54},"これを TBDR \u003Ccode>imageblock_data\u003C\u002Fcode> で書き直すには:",{"type":48,"ordered":56,"items":57},true,[58,59,60,61],"\u003Cstrong>render pipeline state\u003C\u002Fstrong> への移行: compute shader → fragment shader, color attachment 配置, tile rendering pass 構築","\u003Cstrong>\u003Ccode>imageblock_data\u003C\u002Fcode> ピクセル間共有\u003C\u002Fstrong>: Apple Silicon GPU の TBDR (Tile-Based Deferred Rendering) で、各 tile (32x32 px 程度) 内のフラグメントが local memory を共有できる仕組み","\u003Cstrong>入出力 buffer\u002Ftexture の re-binding\u003C\u002Fstrong>: 既存 trainer は MTLBuffer ベース、TBDR pass は MTLTexture ベースで attachment 配置必要","\u003Cstrong>既存テスト 23 件への影響\u003C\u002Fstrong>: SSIM forward\u002Fbackward の数値一致テストが render pipeline でも保てるか再検証",{"type":42,"text":63},"期待効果と risk",{"type":48,"items":65},[66,67,68,69],"\u003Cstrong>期待効果\u003C\u002Fstrong>: SSIM kernel wallclock -50% (Apple 公式 sample で +2-3x speedup を主張)、Phase 5 trainer 全体 -3〜5% (現状 SSIM は ~10% of iter time)","\u003Cstrong>risk\u003C\u002Fstrong>: render pipeline は forward しか書きやすくない (backward の adjoint を fragment shader で書くのは tricky)","render pass 内で gradient buffer に書き戻すには \u003Ccode>texture_load_atomic\u003C\u002Fcode> 系 API、Apple Silicon でしかサポートされない","PSNR drift が出る可能性 (TBDR は accumulate 順序が compute と異なる、A.10 で見た GPU 非決定性問題と類似)",{"type":42,"text":71},"実装するなら必要な手順",{"type":48,"ordered":56,"items":73},[74,75,76,77,78,79],"\u003Ccode>splat-metal\u002Fsrc\u002Fkernels\u002Fssim.rs\u003C\u002Fcode> を別 trait に切り出し (compute backend, tbdr backend を select 可能に)","\u003Ccode>splat\u002Fshaders\u002Floss\u002Fssim_tbdr.metal\u003C\u002Fcode> を新規作成、fragment + imageblock_data","\u003Ccode>MTLRenderPipelineState\u003C\u002Fcode> の構築 (現状ない)、color attachment \u002F depth-stencil の用意","backward pass の TBDR 化 (adjoint computation を fragment shader で再現)、または compute 維持の hybrid 路線","cargo test (cpu reference との数値一致)、smoke run (PSNR drift < 0.05 dB)","30k bench + (期待 -3-5% wallclock vs M-3.x baseline 23m13s)",{"type":42,"text":81},"卒論への含意",{"type":45,"text":83},"第 3 軸 (Apple Silicon 固有最適化) で、当初 \u003Ccode>#5.34\u003C\u002Fcode> として候補に挙げていたが、scope 過大で defer。卒論には「Apple Silicon の TBDR は固有機構として PSNR-neutral な速度向上の余地があるが、本研究の trainer は compute pipeline 構成 (M-3.x baseline) で動作しているため、render pipeline への移行が前提条件。今後の研究課題」と書く。",{"type":37,"label":85,"variant":39,"text":86},"Stretch goal","卒研後の修論 \u002F 追研究フェーズで再着手候補。",{"type":42,"text":88},"関連",{"type":48,"items":90},[91,92,93],"A.10 Kahan finding (compiler 最適化問題): \u003Ccode>a-10-kahan-negative.md\u003C\u002Fcode>","A.5 final ablation 表 第 3 軸 row \"A.1 SSIM タイルシェーダ\": \u003Ccode>final-ablation-table.md\u003C\u002Fcode>","Apple 公式 TBDR sample: \u003Ccode>https:\u002F\u002Fdeveloper.apple.com\u002Fdocumentation\u002Fmetal\u002Fcustomizing_render_pass_setup\u003C\u002Fcode>",[],[96],{"id":26,"title":97,"date":9,"status":10,"polarity":12,"category":98,"axes":99,"tags":100,"task_code":105,"related_runs":106,"delta_psnr":108,"delta_wallclock":109,"rank":110,"verdict":111,"impact_summary":112,"detail_path":113},"A.10 Kahan summation — Metal compiler が compensator を最適化消去","experiment",[14],[16,101,102,103,104],"kahan","metal-compiler","variance","msl","A.10",[107],"lego-sh3-30k",0,"+0.5% (overhead のみ)","low","rejected","Neumaier compensated summation の compensator term は MSL compiler の algebraic optimization で消去され、loss は bit-identical。Kahan は wallclock overhead だけ残し variance reduction 効果ゼロ。","\u002Ffindings\u002Fa-10-kahan-negative\u002F",1782449788615]